Dynamics of Analog Logic-Gate Networks for Machine Learning

We describe the continuous-time dynamics of networks implemented on Field Programable Gate Arrays (FPGAs). The networks can perform Boolean operations when the FPGA is in the clocked (digital) mode; however, we run the programed FPGA in the unclocked (analog) mode. Our motivation is to use these FPGA networks as ultrafast machine-learning processors, using the technique of reservoir computing. We study both the undriven dynamics and the input response of these networks as we vary network design parameters, and we relate the dynamics to accuracy on two machine-learning tasks.